- ixp1200 - lists.cs.princeton.edu

IXP1200 or IXF440 maximum MTU
by Tim Stevens 04 Mar '04

04 Mar '04

Hi, Can anyone tell me whether the IXP1200 boards (ours=ENP-2505) are capable of processing ethernet frames larger than 1500 bytes? Or is the IXF440 the limiting factor? I'm asking this because it might be practical to implement VLAN tagging 802.1Q (this adds 4 bytes to an ethernet frame) or other layer 2 features. Thanks. Kind regards, Tim

1 0

Execution Time Measurement in IXP1200 via gettimeofday
by Jo Ueyama 03 Mar '04

03 Mar '04

Hi All, I am trying to measure the execution time (via C/C++ gettimeofday) of applications running on the StrongARM but I am not being able to measure it properly. Basically, in 10/20% of the executions, gettimeofday is outputing time (in miliseconds) that is out of order (i.e. sometimes it outputs time lower than the previous one resulting in a negative time difference). Let me mention that the same code runs nicely on the PC. Has anyone ever come across such situation? How do you all normally measure execution time in the IXP1200 board? Thanks a lot in anticipation. Regards, -Jo'

1 0

RE: [ixp1200] Receiving Data from a particular port on IXP2400
by David Mentre 01 Mar '04

01 Mar '04

Hello Sanjay, > From: Sanjay Kumar [mailto:ksanjay@cc.gatech.edu] > Sent: Friday, February 27, 2004 11:27 PM > I am writing a microengine rx/tx driver for ixp2400. for the > receive side, > i want to allocate a particular thread for particular MAC > port. > All I could find out was that MSF's receive status word (RSW) > contains a > field which tells which physical port this mpacket came from (e.g. in > POS-PHY Level 3, 32 bit MPHY mode, the 5 LSB bits of RSW0 > will tell this > information). and then it is the thread's job to read this > field and sort > out different mpackets received from different ports. This > will make the > driver pretty messy especially if you are employing multiple > threads to > receive mpackets from a particular port. >From my own reading of Intel docs, you can't wait on a given logical port, only for a physical port, for example in SPHY-4 mode. Why not reuse Intel design, i.e. one full micro-engine (8 threads) that receives from all ports? You could modify this block to output assembled network packets to different scratch ring if you want to have port differentiation. In my opinion (but I may be wrong), Intel engineers have optimized receive block for performance and it would be hard to do a better job. Sincerely yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

1 0

Receiving Data from a particular port on IXP2400
by Sanjay Kumar 27 Feb '04

27 Feb '04

Hi Folks, I am writing a microengine rx/tx driver for ixp2400. for the receive side, i want to allocate a particular thread for particular MAC port. I want that, when I enqueue this thread into RX_THREAD_FREELIST, the thread should be able to specify in which port's mpacket data it is interested in, and the MSF should send a signal to the thread only when an mpacket from that particular port arrives. However, I have not been able to find out any way in which the thread can specify in which port's mpakcet it is interested. (i.e. the equivalent of 3 LSB bits of Receive Request (RCV_REQ) Register in IXP1200 IX bus interface). Is it possible to do that? If someone knows the answer, please let me know. All I could find out was that MSF's receive status word (RSW) contains a field which tells which physical port this mpacket came from (e.g. in POS-PHY Level 3, 32 bit MPHY mode, the 5 LSB bits of RSW0 will tell this information). and then it is the thread's job to read this field and sort out different mpackets received from different ports. This will make the driver pretty messy especially if you are employing multiple threads to receive mpackets from a particular port. Thanks in advance for any input. Sanjay -- ----------------------- http://www.cc.gatech.edu/~ksanjay

1 0

RE: [ixp1200] quad_gbeth_2401
by David Mentre 24 Feb '04

24 Feb '04

Hello Liang, > From: Liang Jian [mailto:ixp2xxx@yahoo.com] > I use SDK quad_gbeth_2401 simulation mode have error, who used it > can you help me? The habit with such a mailing list is to present an issue or an information on the list, with all possible technical details available to you. After that, you'll see if one list reader can answer your question. If you want a personal help, ask your Intel representative or use Intel dedicated web sites (like premier.intel.com). Yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

2 1

How to Ensure Microcode Executes in the Correct Order?
by Jo Ueyama 24 Feb '04

24 Feb '04

Hi All, I am trying to run a Microcode program (code below) that reads one value stored in a *specific* address of the scratch memory and adds this value to anohter one (e.g. 0x1100AB88), storing its result on the same address of the same scratchpad. In 90% of the executions it runs alright, HOWEVER in 10% of the cases it jumps straightly to the write scratch instruction (without performing the alu operation). My question is: What instruction/switch do I need to add in order to ensure that instructions in microcode are carried in the correct order? In the code below the alu instruction MUST be performed *after* scratch read finishes AND *before* write scratch is carried out. Any ideas? Many thanks? -Jo' #include "stdmac.uc" .local zero gpr1 $xfer immed32[gpr1, 0x1100AB88] immed32[zero, 0x0] scratch[read, $xfer, zero, 0, 1], ctx_swap, defer[1] alu[$xfer, $xfer, +, gpr1] scratch[write, $xfer, zero, 0, 1], ctx_swap .endlocal

2 1

RE: [ixp1200] How to Ensure Microcode Executes in the Correct Ord er?
by David Mentre 18 Feb '04

18 Feb '04

Hello Jo, > From: Jo Ueyama [mailto:ueyama@comp.lancs.ac.uk] > Sent: Tuesday, February 17, 2004 7:05 PM > Even though I am using ixp1200 (as quoted by Jimm), I'd > like to try > the signal on my code. > BTW, did you mean Microcode Programmer's Reference Manual > by quoting > "Intel Programmers Reference"? Yes, but I did nto take care and I was refering to IXP2400 version of this manual. > I was trying to locate the > .sig directive > but I couldnt find it. Would you mind ensuring the right > manual so that > I could find out the proper syntax for .sig directive? I think .sig is specific to IXP2xxx. It is one of the architecture redesign between ixp12xx and ixp2xxx. On ixp1200, you have only one signal per functionnal unit. So you need to wait on those specific signals, separetly. Sorry to have given wrong information. Looking back at you original code, the really annoying point, as underlined by Jim, is that your are doing an ALU operation on the register *before* being sure the source register is correclty loaded, due to the defer token (alu operation is executed *before* the context swap that should wait for scratch transfer completion occurs). The ctx_swap operation gives CPU to other threads and returns only after operation completion. So you really need to suppress this defer token to have a working code. Hope I'm not saying stupid things this time, Yours, d. -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

1 0

please, Answer me!!!
by paragon 18 Feb '04

18 Feb '04

Hello, all !!! Where is sram or dram base address in enp-2611? Now. I was tested to following. #define BUF_SRAM_BASE 0x80000000 #define BUF_SDRAM_BASE 0x00000000 Is it problem? Please, answer me~~~ Thanks in advance.

1 0

[ixp2400] Trasmit control word in TX?
by paragon 17 Feb '04

17 Feb '04

Hello~ I don't understand to following. ---------------------------- Writing the Transmit control word. MSF_TBUF_CONTROL_BASE is associated with TBUF element. I thought MSF_TBUF_CONTROL_BASE + tbuf_element, But MSF_TBUF_CONTROL_BASE + (tbuf_element <<3) in IXP2400/2800 Programming chapter 5 Um... What is reason about tbuf_elemnt <<3? Please, advice me~ ref. MSF_TBUF_CONTROL_BASE = 0x1800 Thanks.

1 0

RE: [ixp1200] How to Ensure Microcode Executes in the Correct Ord er?
by Elsenbeck, Jim 17 Feb '04

17 Feb '04

Since his question may have been an ixp1200 (and not ixp2xxx) he really just wants to remove the defer[1]. jim -----Original Message----- From: David Mentre [mailto:Mentre@tcl.ite.mee.com] Sent: Tuesday, February 17, 2004 11:27 AM To: 'IXP1200 Developer's List' Subject: RE: [ixp1200] How to Ensure Microcode Executes in the Correct Ord er? Hello Jo, > From: Jo Ueyama [mailto:ueyama@comp.lancs.ac.uk] > Sent: Tuesday, February 17, 2004 5:06 PM > What instruction/switch do I need to add in order to ensure that > instructions in microcode are carried in the correct order? > In the code > below the alu instruction MUST be performed *after* scratch read > finishes AND *before* write scratch is carried out. > Any ideas? You must use a signal to wait for the read to be done. More specifically: > #include "stdmac.uc" > > .local zero gpr1 $xfer .sig sig_scratch > > immed32[gpr1, 0x1100AB88] > immed32[zero, 0x0] > > scratch[read, $xfer, zero, 0, 1], ctx_swap, defer[1] ;; replace above line with: scratch[read, $xfer, zero, 0, 1], sig_done[sig_scratch] ctx_arb[sig_scratch] ;; after that point, you'll be sure that read is done > alu[$xfer, $xfer, +, gpr1] > scratch[write, $xfer, zero, 0, 1], ctx_swap > .endlocal I've not compiled that code, so I may I made a typo or forgotten something. Signals are used at length in Intel microcode. You should absolutely read Intel manuals if you want to do serious IXP programming. Look at Intel Programmers Reference, sect. 2.8, registers & signals. Yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer.

1 0

RE: [ixp1200] How to Ensure Microcode Executes in the Correct Ord er?
by David Mentre 17 Feb '04

17 Feb '04

Hello Jo, > From: Jo Ueyama [mailto:ueyama@comp.lancs.ac.uk] > Sent: Tuesday, February 17, 2004 5:06 PM > What instruction/switch do I need to add in order to ensure that > instructions in microcode are carried in the correct order? > In the code > below the alu instruction MUST be performed *after* scratch read > finishes AND *before* write scratch is carried out. > Any ideas? You must use a signal to wait for the read to be done. More specifically: > #include "stdmac.uc" > > .local zero gpr1 $xfer .sig sig_scratch > > immed32[gpr1, 0x1100AB88] > immed32[zero, 0x0] > > scratch[read, $xfer, zero, 0, 1], ctx_swap, defer[1] ;; replace above line with: scratch[read, $xfer, zero, 0, 1], sig_done[sig_scratch] ctx_arb[sig_scratch] ;; after that point, you'll be sure that read is done > alu[$xfer, $xfer, +, gpr1] > scratch[write, $xfer, zero, 0, 1], ctx_swap > .endlocal I've not compiled that code, so I may I made a typo or forgotten something. Signals are used at length in Intel microcode. You should absolutely read Intel manuals if you want to do serious IXP programming. Look at Intel Programmers Reference, sect. 2.8, registers & signals. Yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

1 0

halMeDrv.o micro-engine module problem in ENP-2611(IXP2400)?
by smiley 16 Feb '04

16 Feb '04

HI~~! halMeDrv.o micro-engine module problem in ENP-2611(IXP2400)? It was happened warning message in microEngine module when make module. /tmp/ccp3Lko3.s: Assembler messages: /tmp/ccp3Lko3.s:2365: Warning: .space repeat count is zero, ignored what do you mean to upper? Thanks for me!!!

1 0

Do you know send to packet in PCI?
by paragon 16 Feb '04

16 Feb '04

Hello! Help need! Please~~ I don't know send to packet in PCI. I need to process PCI from RX in enp-2611. Send to packet in PCI through scratch ring ? Do you know PCI process logic? Ref. PCI bridge chip is Intel PCI21555. Thanks for me!

1 0

RE: [ixp1200] File info from nfs?
by David Mentre 16 Feb '04

16 Feb '04

Hello Øyvind, > From: Øyvind Hvamstad [mailto:oyvindh@ifi.uio.no] > Sent: Monday, February 16, 2004 9:47 AM > Thanks, I have linux on the card. The thing that trew me off > was that I > had to use #include <sys/stat.h> and not the unix syscalls.h. Maybe an issue related to the compiler? Missing include files? > Sorry if I wasted your time. No worry. Just give more information next time. :) Yours, d. -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

1 0

Video transcoding on IXP1200
by Mohammad Shorfuzzaman 16 Feb '04

16 Feb '04

Hi, I am working on in-network adaptation of media streams. We know about JMF (Java Media Framework- an API for using time-based media into Java applicaitons), which is used for capturing, processing (modifying), and presenting media data streams. Like JMF, Is there any C (microengine C) or low-level code (microcode) for media processing that runs on IXP1200; specifically I mean any code for vedio transcoding on IXP1200. Please help me if anybody has any idea. Regards, Shorfuzzaman ------------------------------------------------- This mail sent through IMP: http://horde.org/imp/

2 1

RE: [ixp1200] File info from nfs?
by David Mentre 16 Feb '04

16 Feb '04

Hello, > From: Øyvind Hvamstad [mailto:oyvindh@ifi.uio.no] > I'm writing a program, where I need the sizes of files. In > linux I would > call the function stat() to fetch this information. What > function would > I call on the strongARM? Without detailed explanation from your side (which platform, which OS, ...), I can only guess. If you are using the software framework provided by Intel in IXP1200, you have the choice between Linux and VxWorks. If it is Linux, use your standard stat() syscall. Otherwise (VxWorks or bare-bone code on the processor), you are on your own. Yours, d. -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

2 1

RE: [ixp1200] Help needed
by David Mentre 13 Feb '04

13 Feb '04

Hello sharmila, > From: sharmila radhakrishnan [mailto:shar_mila2002in@yahoo.co.in] > How to pass exceptional packets from the microengine to the > StrongArm.Can I use SDRAM & SRAM as we would do for > communication between microengines? I think so. You can also use scratch rings in scratch memory to exchange messages. > Since the address space > for StrongArm & Microengines are different do I need to do > the address translation myself? Intel provides certain facility to do that. Look at halMe_GetVirAddr() and following fonctions in XScale(tm) Support Libraries Reference Manual (IXP2400_IXP2800SRM.pdf) > I have one more doubt.Is it necessary to follow the ACE > programming framework for developing applications to download > the code on to the IXP1200 kit and make the code run? No. You can write your own code to download microcode into micro-engines. But, much simpler than that, Intel provides an Hardware Abstraction Layer (HAL) that allows you to do that. Look at UcLo - Microcode Loader Library, in the same manual as above. Yours, d. -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

1 0

Help needed
by sharmila radhakrishnan 13 Feb '04

13 Feb '04

Hello All, How to pass exceptional packets from the microengine to the StrongArm.Can I use SDRAM & SRAM as we would do for communication between microengines?Since the address space for StrongArm & Microengines are different do I need to do the address translation myself?I would be very thankful if you'll could help me out with this. I have one more doubt.Is it necessary to follow the ACE programming framework for developing applications to download the code on to the IXP1200 kit and make the code run? Thanks in advance, Regards, Sharmila Yahoo! India Education Special: Study in the UK now.

1 0

ENP-2611 board PCI-to-PCI bridge testing problem!
by smiley 12 Feb '04

12 Feb '04

question ? ~~~! Since I still could not load the module, I changed hhnet_drawb.c. ---from---- #define DRAWB_CFG_SETUP_DS3 0xB8 #define DRAWB_CFG_CHIP_CONTROL_1 0xCE #define HHNET_DRAWB_MEM_SIZE (1024 * 1024) if (primary) { ... bar = 4; irq_handler = hhnet_drawb_intr_primary; } ---to---- #define DRAWB_CFG_SETUP_DS3 0xAC #define DRAWB_CFG_CHIP_CONTROL_1 0xCC #define HHNET_DRAWB_MEM_SIZE (4 * 1024) if (primary) { ... bar = 0; irq_handler = hhnet_drawb_intr_primary; } --- After the modification, I COULD load the module on both side, server, and ENP. But still I could not make them to communicate. The dmesg & PCI info from the server side----------------- <dmesg> hhnet_drawb: mem_paddr = fe6b0000 hhnet_drawb: mem virt = f89d900 <pci> 03:08.0 Bridge: Intel Corp.: Unknown device b555 (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Interrupt: pin A routed to IRQ 24 Region 0: [virtual] Memory at fe6b0000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at 2400 [size=256] Region 2: [virtual] Memory at fe500000 (32-bit, non-prefetchable) [size=1M] Region 3: Memory at e0000000 (32-bit, prefetchable) [size=256M] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [e4] Vital Product Data Capabilities: [ec] #06 [0080] The dmesg & PCI info from the ENP side----------------- <dmesg> hhnet_drawb: mem_paddr = 00000000 hhnet_drawb: mem virt = cb687000 <pci> Bus 0, device 1, function 0: Bridge: PCI device 8086:b555 (Intel Corp.) (rev 2). IRQ 41. Non-prefetchable 32 bit memory at 0xe4000000 [0xe4000fff]. I/O at 0x100000 [0x1000ff] As you can see, the mem_paddr of ENP is set as 00000000. I think this is the reason of the problem. I think the correct value is "0xe4000000". Am I correct? If then, how do I fix it? Thank you in advance. Regards, EunYoung Joo

2 1

ENP-2611 board PCI-to-PCI bridge testing problem!
by smiley 12 Feb '04

12 Feb '04

ENP-2611 board PCI-to-PCI bridge testing problem! 1. I downloaded the ENP_SDK_3.1_release3 for the PCI-to-PCI bridge communication. 2. I compiled it as described in ch. 6 in "ENP Software Development Kit Programmer's Guide". 3. The document said to load the modules in this manner. - insmod hhnet_eth insmod hhnet insmod hhnet_drawb ifconfig pci0 192.168.111.1 - When I load the module, the following message is displayed. - host/hhnet_drawb.o: init_module: No such device Hint: insmod errors can be caused by incorrect module parameters, including invalid IO or IRQ parameters - The output of "dmesg", is shown like this. - hhnet_drawb: Downstream setup 3 configuration invalid. (b:d:f = 3:8:0) - The host pci info is like below and it seems everything is configured correctly. - Bus 3, device 8, function 0: Bridge: PCI device 8086:b555 (Intel Corp.) (rev 2). IRQ 24. Non-prefetchable 32 bit memory at 0xfe6b0000 [0xfe6b0fff]. I/O at 0x2400 [0x24ff]. Non-prefetchable 32 bit memory at 0xfe500000 [0xfe5fffff]. Prefetchable 32 bit memory at 0xe0000000 [0xefffffff]. - When I look at the source code, In the function "hhnet_drawb_open_dev", you compare the setup value of "pci_read_config_dword()" and HHNET_DRAWB_MEM_MASK, and it seems like the setup value of the "pci_read_config_dword()" is zero. I guess this is the main reason for this problem. I also saw the same problem on the "target" side. What do I have to do to fix this problem?

1 0

RE: [ixp1200] File info from nfs?
by David Mentre 12 Feb '04

12 Feb '04

Hello Øyvind, > From: Øyvind Hvamstad [mailto:oyvindh@ifi.uio.no] > Sent: Wednesday, February 11, 2004 7:13 PM > Hi, I wonder how I might get file info, such as size from the > nfs mount > on the ixp1200. Is there something like the syscall stat(file, buf) > available? I don't understand your question. NFS mounts are seen as regular file system on Linux, so you can use usual Unix tools to get file size, access permission, etc. Yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

2 1

RE: [ixp1200] [In ixp2400/2800 programming] chapter 5. nextblock?
by David Mentre 12 Feb '04

12 Feb '04

Hello, > From: paragon [mailto:commoon@wins21.com] > Present, not trasmitted from RX to TX in enp-2611(ixp2400). > > To see in chapter 5, > 373 immed32(dl_next_block, SPI4_RX_NEXT_BLOCK) > > What's Nextblock? dl_next_block is a context sensitive registers that stores the identifier of the next microblock to which send the packet. It is used within the dl_sink[] macro, in Rx microblock. > #define SPI4_RX_NEXT_BLOCK 0x24 > > what's difference in ixp2400? I don't understand your question. > In chapter 5, what's difference between ixp2400 and ixp2800? > How to modify in chapter.5 ? Basically, the SPI4 mode does not exist on IXP2400. You should rewrite configurations steps. Maybe other things should be also changed. I don't know more as I haven't look at the code provided with the book. If you want to program on IXP2400, you'd rather start from SDK reference designs. You will find several designs on SDK Application CD-ROM. If you don't have it, ask your Intel representative. Yours, d. -- David MENTRE <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

1 0

[In ixp2400/2800 programming] chapter 5. nextblock?
by paragon 12 Feb '04

12 Feb '04

Hello. Dear ixp1200. Present, not trasmitted from RX to TX in enp-2611(ixp2400). To see in chapter 5, 373 immed32(dl_next_block, SPI4_RX_NEXT_BLOCK) What's Nextblock? #define SPI4_RX_NEXT_BLOCK 0x24 what's difference in ixp2400? In chapter 5, what's difference between ixp2400 and ixp2800? How to modify in chapter.5 ? thank you~~^^.

1 0

[ixp2400] RX flow question ?
by paragon 11 Feb '04

11 Feb '04

Hi~~^^ I don't understand to following step! chapter 5 ixp2400/2800 programming original source --------------------------------------- _spi3_rx_move_rbuf_to_dram(rsw.w1.parts.element, cur_mpacket_addr, rsw.w1.parts.byte_count, &rbuf_to_dram_sig); // Update the buffer length dlMeta.bufferSize += rsw.w1.parts.byte_count; // Wait for the mpacket to move into DRAM __wait_for_all(&rbuf_to_dram_sig); _spi3_rx_free_rbuf(rsw.w1.parts.element); // If this is the EOP mpacket then return if (rsw.w1.parts.eop) { break; } // Update the reassembly pointer cur_mpacket_addr += rsw.w1.parts.byte_count; --------------------------------------- I think so to follow. --------------------------------------- _spi3_rx_move_rbuf_to_dram(rsw.w1.parts.element, cur_mpacket_addr, rsw.w1.parts.byte_count, &rbuf_to_dram_sig); __wait_for_all(&rbuf_to_dram_sig); dlMeta.bufferSize += rsw.w1.parts.byte_count; cur_mpacket_addr += rsw.w1.parts.byte_count; if (rsw.w1.parts.eop) { break; } _spi3_rx_free_rbuf(rsw.w1.parts.element); --------------------------------------- what do you think about? Thank you so much in advance!

1 0

File info from nfs?
by Øyvind Hvamstad 11 Feb '04

11 Feb '04

Hi, I wonder how I might get file info, such as size from the nfs mount on the ixp1200. Is there something like the syscall stat(file, buf) available? -- Øyvind Hvamstad <oyvindh(a)ifi.uio.no>

1 0