KP,
A Microengine can interupt the SA Core by performing a fast_wr instruction
to the IREG register. Here is some microcode to do this:
Sv_Ack#:
;Calculate mailbox address
immed[thread_mb_base, UTHREAD_TO_CORE_MAILBOXES]
alu[to_core_mb, thread_mb_base, +, my_thread_id, <<2]
;Format a message and write to shared memory location
alu[reply, reply, OR, format, <<28] ; insert format
alu[$xfer0, --, B, reply]
alu[indirect_wr_len, format, OR, 0x10] ; setup word count
alu[indirect_wr_len, --, B, indirect_wr_len, <<16]
sram[write, $xfer0, to_core_mb, 0, 1], indirect_ref, ctx_swap
;Signal Core by writing to IREG
fast_wr[1, ireg]
For the Core code, there is only one interrupt routine registered to the
operating system. Secondary interrupt handler functions are registered with
this first layer function that handle specific interrupts. The Interrupt
handler demux parses the interrupt vector to determine which of the
secondary functions to call to actually do something with the interrupt. In
the case above, the debug interrupt handler might be called when bit 24 is
set in the IREG register or the thread interrupt handler is called when one
of the bits 0:23 are set in IREG.
I hope this helps!
Eric Heaton
Technical Marketing Engineer
Intel Corporation - NPBU
-----Original Message-----
From: paramesh [mailto:paramesh@trinc.com]
Sent: Thursday, January 03, 2002 11:28 AM
To: ixp1200(a)CS.Princeton.EDU
Subject: [ixp1200] Query
Hi,
Can anyone of you make me sense on the usage of interrupt handling on
StrongArm(SA) side over Vxworks with IREG for FIQ interrupts from
microengine plz..
Best Regards
KP
