July 2004 - ixp1200 - lists.cs.princeton.edu

how to extract the src & dest address....
by nitin makhija 31 Jul '04

31 Jul '04

hellow, Anyone cud. pls tell em how can i extract Dest. and src Ip and Port from a received pkt.. i'm trying to find out this frm eg. code of chapter 8 (Bridging eg. using hashing) in tht they have not even recived the mpackets frm RFIFO, neither the header have being read frm the sdram??? so how can they simply compare the dest. and src. Mac address for bridging..... i've also tried to understand the layer 3 forw. eg: but not sucedde in tht too... according to me following steps shd. be taken to compare any info frm the mpacket... 1. receive mpkt. from RFIFO into SDRAM. 2. then do sdram_read appropriate longwords, at the offset u require to read from say a 28 byte offset to read src. ip adress... 3. then perform the appropriate masking to get the required data .. I'm tring to include a code just to extract the header info, in the code of chapter 3( simple count eg. to have a feel of it) but even not suceeded in it. i was tring out this.... where buf_handle is the starting adress where the mpkt is stored in the sdram, and iphead is the pointer to a structure which has 2 unsigned integer as members..(just to take out a 64 bit value at a particular offset from start address)......just to being wd.... sdram_read(__declspec(sdram_read_reg) *iphead,volatile __declspec(sdram) * (buf_handle + 2) ,1,queue_default,ctx_swap); but this code is also giving an error.... \Study\Project_IXP\test_nitin\Chapter05\receive.c(206): error : expected an expression Sorry if i'm sounding stupid.....not able to find a proper documentation anywhere...if any of u has a sloution to this pls.. reply . By teh way vijay ive already subscribed to pricenton uni. mailing list...Thaxs for tht too .. regards, Nitin Makhija

1 0

RE: [ixp1200] how to extract the src & dest address....
by Johnson, Erik J 30 Jul '04

30 Jul '04

Hi Nitin Yes, that is a known problem. You can find the answer (as well as other errata!) at the following URL: http://intel.com/intelpress/ixp1200/errata.htm Specifically, look for the ZIP file link about half way down the page. Let me know if you still have problems. erik ~~~~~~~~~~~~~~~~~~~~~~~~ Erik J. Johnson erik.j.johnson(a)intel.com Not speaking for Intel ~~~~~~~~~~~~~~~~~~~~~~~~ -----Original Message----- From: ixp1200-bounces(a)lists.cs.princeton.edu [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of nitin makhija Sent: Friday, July 30, 2004 1:03 PM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] how to extract the src & dest address.... Hellow, i'm trying to run the example program of chapter-8 of book by Eric Johnson, but getting the following error's during compilation: Compiling for bridging-latency.list... C:\IXP1200_Programming CD\Chapter08\bridging-latency.c(51): error : intrinsic data buffer "hashInputSrc_93$1$1" cannot be read C:\IXP1200_Programming CD\Chapter08\bridging-latency.c(66): error : intrinsic data buffer "hashInputDst_93$1$1" cannot be read i have even checked "ixp.h" file and there too first parameter to teh hash func. is the input value.... and also cd anyone tell me how can i extract the destination & source ip adress frm the received pkt's....i have the starting adress of sdram where tht pkt. is stored??? i was tring out this.... where buf_handle is the starting adress iphead is the pointer to a structure which has 2 unsigned integer as members.. sdram_read(__declspec(sdram_read_reg) *iphead,volatile __declspec(sdram) * (buf_handle + 2) ,1,queue_default,ctx_swap); but this code is also giving an error.... \Study\Project_IXP\test_nitin\Chapter05\receive.c(206): error : expected an expression actually i want to extract src & dest. IP address alongwd. the port numbers.....and not able to do tht......if anyone of u know ...do help me out Regards, Nitin Makhija _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

1 0

Re: [ixp1200] microACE programming model
by nitin makhija 30 Jul '04

30 Jul '04

Hi Apparao, Its(microACE model) not a must if u want to try out some simple programs in the beginning. But later on when u want the whole NP to function in full fledged mode where ur StrongARM is interacting with Microengines and u have complex app in place. Then u need to have some infrastructure to start off... Then these ACEs come handy. (u can always do things without ACEs). Most modules that we need for most apps are available in these(mostly reusable). Its modify, plug and play sort of modules. This is the reply wht. i have got frm one of the frends who is too working on IXP..... Regards, Nitin On Tue, 27 Jul 2004 Apparao kodavanti wrote : >I have just started researching IXP1200 and after >reading some books I am confused about the microace >programming model. Can I use it to code in our lab >that has an intel IXP1200 evaluation board with >Vxworks OS ? >My host machine is a windows NT machine. The books do >not exclusively say but I read in one of the manuals >that, to use microace programming I need to have Linux >OS. Thanks in advance > >Apparao Kodavanti > >===== >Thanks > >Apparao Kodavanti >(719) 598 - 7412 > >__________________________________________________ >Do You Yahoo!? >Tired of spam? Yahoo! Mail has the best spam protection around >http://mail.yahoo.com >_______________________________________________ >ixp1200 mailing list >ixp1200(a)lists.cs.princeton.edu >https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

1 0

how to extract the src & dest address....
by nitin makhija 30 Jul '04

30 Jul '04

Hellow, i'm trying to run the example program of chapter-8 of book by Eric Johnson, but getting the following error's during compilation: Compiling for bridging-latency.list... C:\IXP1200_Programming CD\Chapter08\bridging-latency.c(51): error : intrinsic data buffer "hashInputSrc_93$1$1" cannot be read C:\IXP1200_Programming CD\Chapter08\bridging-latency.c(66): error : intrinsic data buffer "hashInputDst_93$1$1" cannot be read i have even checked "ixp.h" file and there too first parameter to teh hash func. is the input value.... and also cd anyone tell me how can i extract the destination & source ip adress frm the received pkt's....i have the starting adress of sdram where tht pkt. is stored??? i was tring out this.... where buf_handle is the starting adress iphead is the pointer to a structure which has 2 unsigned integer as members.. sdram_read(__declspec(sdram_read_reg) *iphead,volatile __declspec(sdram) * (buf_handle + 2) ,1,queue_default,ctx_swap); but this code is also giving an error.... \Study\Project_IXP\test_nitin\Chapter05\receive.c(206): error : expected an expression actually i want to extract src & dest. IP address alongwd. the port numbers.....and not able to do tht......if anyone of u know ...do help me out Regards, Nitin Makhija

1 0

microACE programming model
by Apparao kodavanti 27 Jul '04

27 Jul '04

I have just started researching IXP1200 and after reading some books I am confused about the microace programming model. Can I use it to code in our lab that has an intel IXP1200 evaluation board with Vxworks OS ? My host machine is a windows NT machine. The books do not exclusively say but I read in one of the manuals that, to use microace programming I need to have Linux OS. Thanks in advance Apparao Kodavanti ===== Thanks Apparao Kodavanti (719) 598 - 7412 __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

1 0

RE: [ixp1200] Control of microengines and threads++
by Johnson, Erik J 24 Jul '04

24 Jul '04

I do not understand this! [erik] That is because I am an idiot =) 1000Mb/s ports take 2 MEs for rx and 1 ME for tx. The 4 10/100Mb/s ports take 1 me for each. So, you should be able to support 2 Gb/s ports, or 16 10/100Mb/s ports, or 8 10/100Mb/s ports plus 1 Gb/s port. Does that make more sense? When you say ingress ACE microblock, do you in fact mean the EthernetIngress macro? (e.g., SlowIngress macro). [erik] Yes. A microblock is really just two macros, and initialization a macro and a "processing" macro. Erik ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Erik J. Johnson Intel Research & Development erik.j.johnson(a)intel.com NOT SPEAKING FOR INTEL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2 1

RE: [ixp1200] Control of microengines and threads++
by Johnson, Erik J 23 Jul '04

23 Jul '04

Going strictly from memory, here is what I remember 1) How are the microACEs distributed among the microengines when using a default configuration file? I am unable to find any documentation on this subject (The ixsys.* files are generally poorly documented :)). The distribution is based on the number, speed, and direction of the interfaces. For each 100Mb/s interface, two microengines are allocated for all microblocks marked as "receive side", and one microengine is allocated for all "transmit side" microblocks. For every 4 10Mb/s interfaces, one microengine is allocate for the receive side and one microengine for the transmit side. 2) How can I control this distribution? Can I give any directives in the configuration file to load an ACE on two engines, or is this done programatically, i.e., when initializing the ace from the core? Again from memory, if you use the ixsys config utility unmodified, then I believe you are limited to the above distributions. However, the ixsys config is simply a utility built on top of the resource manager APIs, so it is possible to write your own ixsys config utility (or modify the existing one) to perform your own custom mapping. 3) How about the number of threads running on the engine? What is the default and how can I control it? The control of the threads per-microengine is embedded in the source code itself. That is, both the resource manager and the ixsys config utility simply load the microengine with a single image and start all threads executing. That said, if you, for example, configured fewer than 4 10Mb/s ports on the receive side microengine, the ingress ACE code would likely kill the execution of some of the threads (however, it has been a very long time since I looked at this code so if this is critical to you, be sure to read the code). 4) Does the IngressACE do any processing of packets, or does it only define the macros that I use in my dispatch loop? According to the design documents and the source the latter seems to be it, but I'd like to be 100% sure. I guess it depends on your definition of "processing". The ingress ACE core component does not process packets. The ingress ACE microblock reassembles mpackets into a single packet and checks the destination MAC address of the packet to ensure the packet belongs to the system. 5) Does anyone know how many cycles it takes the egress to transfer a 1024 byte large packet from SDRAM to the link? :) -Or where can I find information about how the egress really works? I don't know the transfer time. As a shameless plug, if you want to read about transmit on the IXP1200 you could check out the "IXP1200 Programming" book, Chapter 9. erik ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Erik J. Johnson Intel Research & Development erik.j.johnson(a)intel.com NOT SPEAKING FOR INTEL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2 1

Hellow.....
by nitin makhija 23 Jul '04

23 Jul '04

Hellow, I'm using vxworks imaz to boot the target(IXP1200),wd. tornado emulator in windows env..I was facing problem to connect to the target box,now i'm able to connect to the target now, but even now facing problem while intialising it.... just see the output of various windows: #1..... output of the TestTarget@nitin LOG CONSOLE (where nitin is my "host name") tgtsvr (TestTarget@nitin): Fri Jul 23 10:52:05 2004 Checking License ...OK Connecting to target agent... succeeded. Attaching C++ interface... succeeded. Attaching elf OMF reader for ARM CPU family... succeeded. Error: This is not an elf module for the ARM architecture. Error: Object module load failed for C:\IXP1200\BoardSupport\bin\vb/vxWorks Error: loading core symbol table: status = 0x1002e Error during target server core initialization Target Server will exit #2.... output of the hyper-terminal window......Vxwork com port.. Press any key to stop auto-boot... 6 [VxWorks Boot]: p boot device : eeE unit number : 0 processor number : 0 host name : NITIN file name : c:\ixp1200\BoardSupport\bin\vb\vxWorks inet on ethernet (e) : 10.5.19.164 host inet (h) : 10.5.19.163 user (u) : ixp1200 ftp password (pw) : ix1200 flags (f) : 0x0 target name (tn) : TestTarget [VxWorks Boot]: c '.' = clear field; '-' = go to previous field; ^D = quit boot device : eeE0 processor number : 0 host name : NITIN file name : c:\ixp1200\BoardSupport\bin\vb\vxWorks vxWorks inet on ethernet (e) : 10.5.19.164 inet on backplane (b): host inet (h) : 10.5.19.163 gateway inet (g) : user (u) : ixp1200 ftp password (pw) (blank = use rsh): ix1200 flags (f) : 0x0 target name (tn) : TestTarget startup script (s) : other (o) : [VxWorks Boot]: @ boot device : eeE unit number : 0 processor number : 0 host name : NITIN file name : vxWorks inet on ethernet (e) : 10.5.19.164 host inet (h) : 10.5.19.163 user (u) : ixp1200 ftp password (pw) : ix1200 flags (f) : 0x0 target name (tn) : TestTarget Attached TCP/IP interface to eeE0. Attaching network interface lo0... done. Loading... 712620 + 14184 + 67968 Starting at 0x1000... BSP IXP Version: 1.3.141, built on Jun 5 2001, 19:18:11 CPU ID: 6901C123 CPU Speed: 200 MHz Early serial debug initialized muxDevLoad failed for device entry 0! Attached TCP/IP interface to eeE unit 0 Attaching network interface lo0... done. 0x7ffe64 (tRootTask): dc0 - Failed to read ethernet address NFS client support not included. VxWorks Copyright 1984-1998 Wind River Systems, Inc. CPU: Intel ixp1200eb - ARM IXP1200 VxWorks: 5.4 BSP version: 1.2/2 Creation date: Jun 5 2001 WDB: Ready. #3.. output of the ftp window..... It's displaying that the transfer of vxworks(boot imz) is sucessful..... i even tried wd. different vxwork imz, which u mailed me later... if u know why this kinda error is coming do reply.... Regards, Nitin Makhija

1 0

Control of microengines and threads++
by Øyvind Hvamstad 21 Jul '04

21 Jul '04

Hi, thanks for all the help so far, but I still have a few questions (potentially stupid, as always): How are the microACEs distributed among the microengines when using a default configuration file? I am unable to find any documentation on this subject (The ixsys.* files are generally poorly documented :)). How can I control this distribution? Can I give any directives in the configuration file to load an ACE on two engines, or is this done programatically, i.e., when initializing the ace from the core? How about the number of threads running on the engine? What is the default and how can I control it? Does the IngressACE do any processing of packets, or does it only define the macros that I use in my dispatch loop? According to the design documents and the source the latter seems to be it, but I'd like to be 100% sure. Does anyone know how many cycles it takes the egress to transfer a 1024 byte large packet from SDRAM to the link? :) -Or where can I find information about how the egress really works? In advance, thanks! Info: ENP-2505, embedded linux, Intel SDK 2.01 -- Øyvind Hvamstad <oyvindh(a)ifi.uio.no>

1 0

Re: [ixp1200] Creating streams in IXP1200
by dveluchamy＠vsnl.net 12 Jul '04

12 Jul '04

Hi Sunil, Apart from the uEngine code to pull from RFIFO into trasfer registers/DRAM we have to program the Ready Bus Sequencer as well. Check if u have done this. Its a common mistake most beginners do. Thanks, Velu ----- Original Message ----- From: sunil.mekad(a)wipro.com Date: Monday, July 12, 2004 8:31 am Subject: [ixp1200] Creating streams in IXP1200 > Hi everyone, > > I had created streams in IXP1200 workbench for a TCP/IP packet. > Howeverthese packets do not enter the RFIFO even after following > the proper > procedure as give in the IXP1200 Workbench user guide. > > If anyone has tried simulating packet stream tell me if anything else > has to be done? Do I need to write any other script file other > than the > one that intialises the various units of IXP1200? > > Thanks in advance, > > Sunil Mekad > > > -----Original Message----- > From: ixp1200-bounces(a)lists.cs.princeton.edu > [ixp1200-bounces(a)lists.cs.princeton.edu] On Behalf Of > ixp1200-request(a)lists.cs.princeton.edu > Sent: Friday, July 09, 2004 9:30 PM > To: ixp1200(a)lists.cs.princeton.edu > Subject: ixp1200 Digest, Vol 8, Issue 3 > > > Send ixp1200 mailing list submissions to > ixp1200(a)lists.cs.princeton.edu > > To subscribe or unsubscribe via the World Wide Web, visit > https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 > or, via email, send a message with subject or body 'help' to > ixp1200-request(a)lists.cs.princeton.edu > > You can reach the person managing the list at > ixp1200-owner(a)lists.cs.princeton.edu > > When replying, please edit your Subject line so it is more > specific than > "Re: Contents of ixp1200 digest..." > _______________________________________________ > ixp1200 mailing list > ixp1200(a)lists.cs.princeton.edu > https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 >

1 0