- ixp1200 - lists.cs.princeton.edu

who ixp1200.
by Raghunandan, Makaram 23 Oct '03

23 Oct '03

who ixp1200

1 0

Re: [ixp1200] Accessing logical interface information.
by Shyamal Pandya 23 Oct '03

23 Oct '03

>1. Is it possible to get the interface configuration from microcode, >such as the ip address given in the ixsys.config? You could share the ip adress or other info between the strongarm and microengines through scratchpad memory. >2. In the StrongARM code, do I have to use crosscalls to get this >information from the ingressACE, or is there another way? If no other >way, is there an example I could look at on how to use the crosscall? you might look up the ixsys.config file from the strongarm code, but it is probably better to use crosscalls. Don't know about examples, but the SDK reference docs will help. _________________________________________________________________ Concerned that messages may bounce because your Hotmail account has exceeded its 2MB storage limit? Get Hotmail Extra Storage! http://join.msn.com/?PAGE=features/es

1 0

ME-ME Ring
by Christopher S Hall 23 Oct '03

23 Oct '03

I'm trying to write code that passes packets between microengines hopefully using ucode macros provided by the SDK. Right now, I have the Ingress ace running on ME's 0 and 1 (1 Gigabit port), Intermediate processing code on ME's 2, 3, 4, and the Egress ace running on ME 5. I need to pass packets from ME's 0,1 to ME's 2,3,4 (The egress side isn't to important right now). The DL_MESink macro seems to queue the packets up, but I'm unsure how to dequeue the packets at the other end. Can the ME-ME rings provided by the SDK be used for this, and, if so, how are packets dequeued? Thanks, Chris

2 1

RE: [ixp1200] Accessing logical interface information.
by Botham, Mick 23 Oct '03

23 Oct '03

Øyvind, I was referring to the IXF440 manual, this is a promiscuous MAC, the ethernet MAC address is only used for flow control, not to filter packet reception. Rgds -----Original Message----- From: owner-ixp1200(a)CS.Princeton.EDU [mailto:owner-ixp1200@CS.Princeton.EDU] On Behalf Of Øyvind Hvamstad Sent: 21 October 2003 15:24 To: ixp1200(a)CS.Princeton.EDU Subject: [ixp1200] Accessing logical interface information. Hi, I'm using the ENP-2505 1. Is it possible to get the interface configuration from microcode, such as the ip address given in the ixsys.config? 2. In the StrongARM code, do I have to use crosscalls to get this information from the ingressACE, or is there another way? If no other way, is there an example I could look at on how to use the crosscall? 3. I saw in an ealier post, that the mac addr was in the Physical Address Register, I'm unable to find this in my manuals. Could someone guide me there? -- Øyvind Hvamstad <oyvindh(a)ifi.uio.no>

1 0

IXP1200 with Radisys ENP2505
by Edson Barbosa Lisboa 22 Oct '03

22 Oct '03

Hello, I want to connect 2 machines, one with windows2000 and other with Redhat linux 7.3, to the Radidsys ENP2505 board with IXP1200 that it is installed in other machine. The Source machine (windows2000) has the 10.1.0.100 IP address and it is connected in the port1 of the ENP 2505 with 10.1.0.1 IP. The Sink machine (Linux) has the 10.2.0.100 IP and it is connected in the port2 with 10.2.0.1 IP address. I am using L3forward library ACE. However, when I run ping from source machine to sink machine I do not get response. The host is unreachable. Can you help me please ? Best Regards, Edson Barbosa

1 0

How do ME-ME rings work?
by Christopher Hall 21 Oct '03

21 Oct '03

I currently have code loaded and running on the IXP1200 as follows: ME 0-1 are running the FastIngress code (1 gigabit port), ME 2-3-4 are running processing code (packet counting of various sorts), ME 5 is running FastEgress code. Now, I need to be able to send packets from one microengine to another preferably without involving the StrongARM. I'm thinking that the ME-ME ring may provide me with what I need, but I can't see how packets are enqueued and dequeued. The DL_MESink macro seems to enqueue a packet, but there is no corresponding code to dequeue a packet. My understanding so far is that the packet is dequeued by the egress code. Can the ME-ME ring(s) be used (adapted) for passing packets between microengines, or do I need to write my own queue/dequeue code? Thanks, Chris

1 0

Accessing logical interface information.
by Øyvind Hvamstad 21 Oct '03

21 Oct '03

Hi, I'm using the ENP-2505 1. Is it possible to get the interface configuration from microcode, such as the ip address given in the ixsys.config? 2. In the StrongARM code, do I have to use crosscalls to get this information from the ingressACE, or is there another way? If no other way, is there an example I could look at on how to use the crosscall? 3. I saw in an ealier post, that the mac addr was in the Physical Address Register, I'm unable to find this in my manuals. Could someone guide me there? -- Øyvind Hvamstad <oyvindh(a)ifi.uio.no>

1 0

Microcode loading problem.
by 조준우 20 Oct '03

20 Oct '03

I am analyzing Vera source code. But I am blocked at source code of loading the microcode part. Below code is presented at /Vera/IXP1200_Apps/IPmm/main.c Control_BootUEs(&rcv_uCode, &xmt_uCode); But I can't find rcv_uCode, xmt_uCode uEng_uCodeInfo structure variable. From where that varible is declared? I guess that this is related with 'Vera/bin/postuca.pl' file. If above guess is right, plz say loading mechanism simply. if above guess is wrong, plz say exact location. Thanks.

2 3

IXP1200 sending out a flood of packets on port 3
by Christopher George Baron 20 Oct '03

20 Oct '03

After booting up embedded linux on the StrongARM, and assigning MAC addresses to ports 0 through 3, a flood of packets is being sent out of port 3 of the IXP1200. No microengines are doing any processing. I am wondering if anyone else had this problem, or an idea of what it might be. Thanks, Chris

3 2

RE: [ixp1200] How do I get IXP EB's ethernet address?
by Botham, Mick 16 Oct '03

16 Oct '03

It's in the Physical Address Register - see section 3.2.4.3 of the datasheet. -----Original Message----- From: owner-ixp1200(a)CS.Princeton.EDU [mailto:owner-ixp1200@CS.Princeton.EDU] On Behalf Of jwc(a)core.kaist.ac.kr Sent: 16 October 2003 06:03 To: ixp1200(a)CS.Princeton.EDU Subject: [ixp1200] How do I get IXP EB's ethernet address? Hello. I use IXP1200 Evaluation board. I want to know ethrenet(MAC) address of port0. How do I get that ethernet address? Thanks.

1 0

How do I get IXP EB's ethernet address?
by 조준우 16 Oct '03

16 Oct '03

Hello. I use IXP1200 Evaluation board. I want to know ethrenet(MAC) address of port0. How do I get that ethernet address? Thanks.

1 0

How to signal from Pentium to IXP EB?
by 조준우 14 Oct '03

14 Oct '03

Hello. I use IXP1200 EB attached(on PCI slot) to Pentium PC. How can I signal from Pentium PC to MICROENGINE in IXP EB? I searched VERA code to find the method. But I failed to find until now. Is there a good method? Like using some register or using interrupt? I think "polling" method now. Namely, PC writes a flag into SDRAM or SRAM region and MicroEngine check that flag continually. But I think that interrupt is more polished method. ^^ Plz give me any method about signalling from PC to IXP EB. Peformance is most important for my application. Thanks!

1 0

How to signal from Pentium to IXP EB?
by 조준우 13 Oct '03

13 Oct '03

Hello. I use IXP1200 EB attached(on PCI slot) to Pentium PC. How can I signal Pentium PC to MICROENGINE in IXP EB? I searched VERA code to find the method. But I failed until now. Is there a good method? Like using some register or using interrupt? I think "polling" method now. Namely, writing to SDRAM or SRAM region and check that region continually. But I think that interrupt is more polished method. ^^ Anyway plz give me answer. Peformance is most important for my application. Thanks

1 0

configure IXF440 ports
by tstevens 10 Oct '03

10 Oct '03

Hi, In order to investigate the packet loss issue on our ENP-2505 board, we would like to know how we can set the IXF440 ports fixed, thus turning off the autonegotiation. Does anyone know how to configure these (4) ports? Thank you in advance. Kind regards, Tim

1 1

Whered do I get microcode assember?
by 조준우 07 Oct '03

07 Oct '03

Hello Until now, I only use StrongARM on IXP machine. Now, I want to use MicroEngines... But I don't find Microcode assember. I use IXP1200 Evaluation board and have SW development kit CDs. Whered do I get in-line microcode assember? 'In-line' means that assember operates at Linux machine. From SDK CD? or internet? Please answer anything about microcode assember, thanks!

2 1

Where do I get microcode assembler?
by 조준우 07 Oct '03

07 Oct '03

Hello Until now, I only use StrongARM on IXP machine. Now, I want to use MicroEngines... But I don't find Microcode assember. I use IXP1200 Evaluation board and have SW development kit CDs. Whered do I get in-line microcode assember? 'In-line' means that assember operates at Linux machine. Please answer.. thanks!

1 0

DMA transfers to host?
by Øyvind Hvamstad 06 Oct '03

06 Oct '03

Hi. I would like to know how to send data from the ENP-2505s sdram to the host disk. I read from the archive that it is possible to communicate between different pci devices, but I need more information on the subject. What exactly does the pci_dma instruction do? Can I use this to send data to the host? How can I fetch data from the host? -- Øyvind Hvamstad <oyvindh(a)ifi.uio.no>

1 0

packet loss on IXF440 ports
by Koert Vlaeminck 06 Oct '03

06 Oct '03

Hi, Recently, we configured a Radisys ENP-2505 Intel IXP1200 evaluation board (revision C0) running the linux kernel (2.3.99) provided by the Intel IXA SDK. When trying to run the example count application from the Intel IXA SDK 2.01, we noticed the following problems: 1/ when using a 10 mbit hub between the IXF440 ports and the traffic generator (linux host), no data is received in the ENP-2505. Seems like the 10/100 mbit half-/full-duplex autonegotiation does not work properly (10mbit link LED is lit however). 2/ when using a crossover cable between the traffic generator and one of the ports of the ENP-2505 (thus 100 mbit full-duplex), the application seems to work (on that one port of course), but we notice a packet loss (about 20%). The cable is tested between two regular PCs and is fine. Generating packets with ping (without parameters) or with ping -f (more intensive) does not influence the packet loss rate, so sending one or hundred packets each second does not seem to matter. The same problem is encountered with the more advanced examples such as the L3-forwarder, which makes me think the IXA SDK provided Ingress ACEs are not suitable for the ENP boards. Has anyone encountered (and solved) one of these problems? Any help would be greatly appreciated. Kind regards, Tim & Koert

2 1

Re: [ixp1200] WWBump Code in 'Network System Design'
by Shyamal Pandya 04 Oct '03

04 Oct '03

Hi Lim, I don't have this book but let me give it a shot. >1. alu[dpoff, dpoff, +, 16] ; Add Ether+TCP offsets >2. Buf_GetData[base, dl_buffer_handle] ; Get buffer base address >3. DL_GetBufferOffset[boff] ; Get data offset in buf. >4. alu[boff, boff, +, dpoff] ; Compute byte address >5. alu_shf[boff, --, B, boff, >>3] ; Convert to Q-Word addr. >6. sdram[read, $$hdr0, base, boff, 1], ctx_swap ; Read 8 bytes > >Assume the packet reach at the IX_Bus interface. [This is a big >assumption... and is it correct? If not, when dispatch loop runs the WWBump >macro, the entire packet is currently in SDRAM? ] >From the above code it is pretty clear that the packet is already in the SDRAM. There should be code somewhere that handles packet reception and transfer from port --> rfifo --> SDRAM. Since it is pretty generic it should be provided at one place and then not repeated. The dispatch loop must call the Ingress macro which performs the packet reception before it will call the WWBump macro. > >Line 2 get the SDRAM base address for the xfer reg to copy packet data >into. > >Line 3 get the packet offset currently located in buffer (rfifo? SDRAM?), >and i wonder how, by this command, the rfifo (SDRAM?) will know which is >the correct current packet offset to return, amongst so many packets >resided in rfifo (SDRAM?). > The dl_buffer_handle is the buffer handle for one particular packet, and it is set some where before the above code, probably by Ingress. You will have to look at the dispatch loop and follow the macros to understand. The SDRAM doesn't return anything, the offset is calculated by your code that puts the data in the SDRAM in the first place. Look at the code for dispatch loop macros for a better idea. >Assume IP header = 20 bytes, dpoff = 36 bytes. >Line 4 & 5 calculate dpoff and convert to quadword. In this context, SDRAM >should read from 32 - 39 bytes. But, how does the SDRAM knows to read from >32 bytes, instead of 36 bytes?? Is there an internal mechanism to convert?? > Line 5 converts the boff to a quadword, by dividing it by 8 (>>3). So a value of 36 will turn into 4 after line 5. The 4th quadword starts with byte 32. Again, it is your code that is doing the conversion, and no internal mechanism. >Line 6, this line, make me confuse, i assume, this line actually read >packet data from SDRAM into transfer register, where the packet data >offset, is at base+boff. So, the previous assumption --> data is in rfifo >is wrong. Then, which part of the code in WWBump, where microengine >instructs IX-Bus to transfer packet into SDRAM?? > If WWBump doesn't have the code, I guess there is some code (probably EthernetIngress) that does the stuff. Look at the dispatch loop to see what is called before WWBump. That's what I can assume, someone who has the book will be able to shed more light on the code. -- Shyamal Pandya Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 _________________________________________________________________ Share your photos without swamping your Inbox. Get Hotmail Extra Storage today! http://join.msn.com/?PAGE=features/es

1 0

Debugging code running on hardware using developers workbench
by Craig Wampler 04 Oct '03

04 Oct '03

Hi - I was wondering if anyone has successfully used Developer Workbench to debug the ixp hardware (breakpoints, memory watch, etc) running linux. I've looked for a while, but the documentation from the developer's workbench doesn't really tell you what to do if it doesn't work, or how exactly it is supposed to work. If you have gotten it to work, or think that you know how, could you send me detailed directions or point me to some detailed directions. I have tried connecting by putting in the ip address (and I tried dns host name too) of the host that contains the IXP card into the Workbench's hardware options (and I selected to connect over ethernet). I tried it both from several hops away, and from the same switch the IXP is on. When I was on the same switch, I tried connecting both the the computer the IXP card is in, and the IP address who's ARP entry sends packets to the IXP card. Neither works. Our host machine and the StrongARM on the IXP are both running Linux. The machine I'm trying to connect from is running windows XP. If it's not possible to connect over ethernet, does anyone know of a way to connect Developers Workbench to the IXP card using a serial cable, if the card isn't running VxWorks? Thanks in advance, Craig Wampler CS Undergrad GA Tech

1 0

Re: [ixp1200] WWBump Code in 'Network System Design'
by Shyamal Pandya 04 Oct '03

04 Oct '03

When SDRAM is accessed from microengines the address must be quadword (8-byte) aligned. Consider the following two cases: Case I: (minimum IP header length) Assume IP HLEN = 20, dpoff = 14 + 20 + 2 = 36 bytes That is destination port offset will be at byte ofset 36 & 37. The packet data will have to be accessed from byte offset 32 because of the 8-byte alignment requirement. So the first longword contains bytes 32, 33, 34 and 35. The second longword begins with the destination port. also 36 AND 0x7 == 4 Case II: (IP header length 24 bytes) Assume IP HLEN = 24, dpoff = 14 + 24 + 2 = 40 bytes That is destination port offset will be at byte offset 40 & 41. Here the packet data can be accessed from byte 40, so that the first longword contains the destination port. Also 40 AND 0x7 == 0 Hope this clears the doubt. -- Shyamal Pandya Arizona State University Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 >From: Lim Boon Ping <syseeker(a)yahoo.com> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: ixp1200(a)CS.Princeton.EDU >Subject: [ixp1200] WWBump Code in 'Network System Design' >Date: Tue, 30 Sep 2003 23:37:34 -0700 (PDT) > > >Hi all, > >This is a question regarding WWBump example code in 'Network System Design, >using network processors', from Prof. Douglas Comer. > >Trace through the code in WWBump.uc, i have some questions on the section >regarding extracting destination port from SDRAM transfer register. I might >have misunderstood the overall concept behind these codes, and hope if >someone could point out. > >Thanks in advance. > >.... > >/* 'dpoff' contains the offset for destination port in TCP packet,*/ >/* that is 14 bytes Ethernet header + n bytes IP header + 2 */ >/* bytes source port, where n has been calculated earlier. */ > >/* Use lower three bits of the byte offset to determine which */ >/* byte the destination port will be in. If value >= 4, dest. */ >/* port is in the 2nd longword; otherwise it's in the first. */ > alu[ dpoff, dpoff, AND, 0x7 ] ; Get lowest three bits > alu[ --, dpoff, -, 4] ; Test and conditional > br>=0[SecondWord#] ; branch if value >=4 > >FirstWord#: /* Load upper two bytes of register $$hdr0 */ > ld_field_w_clr[dport, 0011, $$hdr0, >>16] ; Shift before mask > br[GotDstPort#] ; Check port number > >SecondWord#: /* Load lower two bytes of register $$hdr1 */ > ld_field_w_clr[dport, 0011, $$hdr1, >>16] ; Shift before mask > >..... > > >May i know why the author uses lower 3 bits of the byte offset to determine >byte the destination port will be in? > >Isnt' dpoff has pointed to the offset of destination port, extracting 8 >bytes from the offset onwards will always start from destination port until >the first 2 bytes of ACK number, (means it will always be in $$hdr0) ? > >Then why must the code check for condition as it will never branch to >SecondWord#? > >If it will branch to SecondWord#, under what condition? > >I have done some calculation, please kindly indicate if i have >misunderstood the concept. > >Case I: (minimum IP header length) > >Assume IP HLEN = 20, dpoff = 14 + 20 + 2 = 36 bytes >That is destination port offset will be at 37 & 38 bytes of the packet. > >36 bytes -> 288 bits -> 100100000 >100100000 & 000000111 = 000000000 /* dpoff AND 0x7 */ >result: branch to FirstWord# > > >Case II: (40 bytes IP header length) > >Assume IP HLEN = 40, dpoff = 14 + 40 + 2 = 56 bytes >That is destination port offset will be at 57 & 58 bytes of the packet. > >56 bytes -> 448 bits -> 111000000 >111000000 & 000000111 = 000000000 /* dpoff AND 0x7 */ >result: branch to FirstWord# > > >Case III: (60 bytes IP header length) > >Assume IP HLEN = 60, dpoff = 14 + 60 + 2 = 76 bytes >That is destination port offset will be at 77 & 78 bytes of the packet. > >76 bytes -> 608 bits -> 1001100000 >1001100000 & 000000111 = 000000000 /* dpoff AND 0x7 */ >result: branch to FirstWord# > > > > > >Best regards, >Lim Boon Ping >--------------------------------------- >Post-Graduate Student >Multimedia University >Cyberjaya, Malaysia > >--------------------------------- >Do you Yahoo!? >The New Yahoo! Shopping - with improved product search _________________________________________________________________ Add MSN 8 Internet Software to your existing Internet access and enjoy patented spam protection and more. Sign up now! http://join.msn.com/?page=dept/byoa

2 1

WWBump Code in 'Network System Design'
by Lim Boon Ping 01 Oct '03

01 Oct '03

Hi all, This is a question regarding WWBump example code in 'Network System Design, using network processors', from Prof. Douglas Comer. Trace through the code in WWBump.uc, i have some questions on the section regarding extracting destination port from SDRAM transfer register. I might have misunderstood the overall concept behind these codes, and hope if someone could point out. Thanks in advance. .... /* 'dpoff' contains the offset for destination port in TCP packet,*/ /* that is 14 bytes Ethernet header + n bytes IP header + 2 */ /* bytes source port, where n has been calculated earlier. */ /* Use lower three bits of the byte offset to determine which */ /* byte the destination port will be in. If value >= 4, dest. */ /* port is in the 2nd longword; otherwise it's in the first. */ alu[ dpoff, dpoff, AND, 0x7 ] ; Get lowest three bits alu[ --, dpoff, -, 4] ; Test and conditional br>=0[SecondWord#] ; branch if value >=4 FirstWord#: /* Load upper two bytes of register $$hdr0 */ ld_field_w_clr[dport, 0011, $$hdr0, >>16] ; Shift before mask br[GotDstPort#] ; Check port number SecondWord#: /* Load lower two bytes of register $$hdr1 */ ld_field_w_clr[dport, 0011, $$hdr1, >>16] ; Shift before mask ..... May i know why the author uses lower 3 bits of the byte offset to determine byte the destination port will be in? Isnt' dpoff has pointed to the offset of destination port, extracting 8 bytes from the offset onwards will always start from destination port until the first 2 bytes of ACK number, (means it will always be in $$hdr0) ? Then why must the code check for condition as it will never branch to SecondWord#? If it will branch to SecondWord#, under what condition? I have done some calculation, please kindly indicate if i have misunderstood the concept. Case I: (minimum IP header length) Assume IP HLEN = 20, dpoff = 14 + 20 + 2 = 36 bytes That is destination port offset will be at 37 & 38 bytes of the packet. 36 bytes -> 288 bits -> 100100000 100100000 & 000000111 = 000000000 /* dpoff AND 0x7 */ result: branch to FirstWord# Case II: (40 bytes IP header length) Assume IP HLEN = 40, dpoff = 14 + 40 + 2 = 56 bytes That is destination port offset will be at 57 & 58 bytes of the packet. 56 bytes -> 448 bits -> 111000000 111000000 & 000000111 = 000000000 /* dpoff AND 0x7 */ result: branch to FirstWord# Case III: (60 bytes IP header length) Assume IP HLEN = 60, dpoff = 14 + 60 + 2 = 76 bytes That is destination port offset will be at 77 & 78 bytes of the packet. 76 bytes -> 608 bits -> 1001100000 1001100000 & 000000111 = 000000000 /* dpoff AND 0x7 */ result: branch to FirstWord# Best regards, Lim Boon Ping --------------------------------------- Post-Graduate Student Multimedia University Cyberjaya, Malaysia --------------------------------- Do you Yahoo!? The New Yahoo! Shopping - with improved product search

1 0

workbench debug error
by Yong Liu 29 Sep '03

29 Sep '03

Hi, everybody I tried to debug microace code on hardware using workbench. When I start debug the l3fwdr example there comes an error: "Attach to debug library operation failed" I know someone asked the same question on this mail list, but I can not find the answer. Anybody can help me? Thanks a lot! BTW, I am using enp-2505 board, embedded linux, ethernet connectiong for debug. I have set the "mode" to 1 in ixsys.config-l3fwdr. The portmapper is started. And when I debug a simple independent micro C code on the microengine, the workbench works very well in the hardware debug mode. Yong Liu

1 0

RE : [ixp1200] how to receive packets on IX Bus
by Veluchamy Dinakaran 29 Sep '03

29 Sep '03

Hi Amit, I too faced the same problem, resolved it now. U should actually program the ready bus sequencer to get the packets into the rfifo(this is basically a 12 byte program) element. U can do this in two ways(may be more), 1) write opcode into rcv_rdy_ctl reg.(see hw_init() in layer3 forwarding example) 2) choose the instructions u want to place in the register from system conf>ix bus interface. Enable bus seq. Click program and select the instructions(see uCLab1 example). and that should do... Bye, D.Veluchamy, College of Engineering,Guindy, Chennai.

1 0

Micro C Compiler
by Øyvind Hvamstad 29 Sep '03

29 Sep '03

Hi, I was planning to use microC when programming the engines, so I was wondering. 1. Has anyone been able to run uccl.exe through wine? (I can't, and vmware isn't cheap) 2. When trying to compile the Bridging example from the IXP Programming book, the file DispachLoop.h is nowhere to be found. Are there some secret library that I need? Or should I already have it? (Couldn't find it) 3. Would you recommend me to use microC instead of microcode? (Any known quirks?) 4. Would using microC involve having to port several microcode blocks? 5. Sorry for the, possibly, stupid questions. Can someone assist me? -- Øyvind Hvamstad <oyvindh(a)ifi.uio.no>

6 6