- ixp1200 - lists.cs.princeton.edu

Re: [ixp1200] Inter-ME uCode communication
by Shyamal Pandya 22 Jul '03

22 Jul '03

I wrote my own MESource macro and I assigned ME-to-ME queues separately. This has to be done carefully so as not to clash with the queues assigned by the resource manager, otherwise you will end up clobbering the queues already set up. I look at the resource manager source code will reveal the queues that are assigned, so that you can determine your own queues. As Abhijeet said, these are hard-coded. Also if you look at the MESink macro, you will realize that the queues in which the packets go depend on the output port, so if you want to put your packets in a different queue you will have to write a different sink macro, or you will have to manilpulate the output port register in the sending thread. -- Shyamal Pandya Arizona State University Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 >From: Cyrus Hall <hallcp(a)cs.colorado.edu> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: ixp1200 List <ixp1200(a)CS.Princeton.EDU> >Subject: [ixp1200] Inter-ME uCode communication >Date: 21 Jul 2003 17:03:09 -0600 > >I've finally gotten to the point in my code where I need to expand to >multiple microengines. I think I've figured out what changes are needed >in ixconfig, but other things are now vexing me. > >In the count example, the dispatch loop either forwards a packet with >DL_SASink[] or DL_MESink[]. From the documentation, it sounds like >DL_MESink[] passes the current packet reference to the next control >block (next microengine). Just like DL_SASink[] has a inverse >(DL_SASource[]), I would expect the the ME version to have one, >something like DL_MESource[], yet no such macro exists. > >So what do must of you do? Have you just written a DL_MESource, or do >you use one of the many other ways to syncronize between engines (SRAM >CAM locks, or some other test-set mechanism)? I'm wondering which is >the best way to go from here. > >Thanks, >Cy > _________________________________________________________________ MSN 8 helps eliminate e-mail viruses. Get 2 months FREE*. http://join.msn.com/?page=features/virus

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FBI error specification.
by Yannis Haritakis 17 Jul '03

17 Jul '03

Hi all, According to hardware reference manual of ixp1200, the FBI should set the SOP bit of receive control register to zero whenever a cancelled speculative request occurs. I am suspecting that this does not occur actually. Has anyone used this feature ? Thanks for your time, yannis

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how to load the application developed with uC to ixp1200
by ning weng 16 Jul '03

16 Jul '03

Hi, Thanks advance if you coud provide me some hint or reference... For an application developed in Micro C code(not microcode) such as the bridging in ixp1200 programming, how do I load it to ixp1200? I guess my question is : is it same with application developed with microcode? Thanks -Ning

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ENP-2505 Bootup
by Ning Weng 14 Jul '03

14 Jul '03

Greeting, Did any one have this kind of experience? Please help and give me some hints. (I do remember some people mentioned in this broadcast e-mail before: one special key to get rid of this problem.) ENP-2505 board booting up... ".... Welcome to minicom 1.83.1 OPTIONS: History Buffer, F-key Macros, Search History Buffer, I18n Compiled on Aug 28 2001, 15:09:33. Press CTRL-A Z for help on special keys cygmon> script "./.ixstart": global timeout ...." Any help is greatly appreciated!!!! Thanks a lot. -Ning

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ix bus throughput limitations
by liam noonan 14 Jul '03

14 Jul '03

Hi, I have carried out some testing on a single thread process receiving and counting packets (code from chapter 5 from ixp 1200 book) When it runs at wire speed at 177Mhz and Ixbus at 66 Mhz it has a receive rate of 350 Mbps at the IX bus. The same rate is achieved when running at 200Mhz, Ixbus at 66Mhz. I would expect the receive rate to be faster. Does anyone have any idea as to why the receive rate isn't higher for 200MHZ? Thanks Liam Noonan Univeristy Of Limerick

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can anybody make it logic??
by rodrigo ruiz 14 Jul '03

14 Jul '03

Hi.. we�ve been working about four months with the enp-2505. We followed the ixa education workstation step by step, after we corrected some poblems, everything worked just fine, except that the card didn`t give response through the serial interface. We think we might detect some hardware problems. We changed the video card (nvidia gforce, agp),for a pci one. The leds start changeing in the booting. Then we completed the instalation according to the guide and the enp-2505 got alive. We got running win 2000 in the virtual machine, Linux 7.2 and the linux in the enp-2505. So far so good. The problem now is that we gotta install the card in some clones, identical machines, and what we get is either linux 7.2 just stop working, or the card sends some lines printing the registers... We changed te hard drive (the one that was working), and didn`t work in the new pc, but the hard drive from the new, worked on the old pc. We are using three computers (exactly the same), and the same hard drive and the same enp2505 only works in one of the computers. We already checked jumpers and bios. They seems to be just the same. In could get into cygmon terminal in some of the pc, with the same hardrive, but the .bootixp doesn`t work on it, only in the only pc it worked. Does anybody knows what is happening or at least has some idea of it ???. thanks Rodrigo __________________________________ Do you Yahoo!? SBC Yahoo! DSL - Now only $29.95 per month! http://sbc.yahoo.com

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The microACE "tutorial"
by Øyvind Hvamstad 11 Jul '03

11 Jul '03

Hi, I'm trying to do the "tutorial" for the ENP-2505 card. The card is up after numerous hours of compiling and tweeking. So now I am ready for some programming; I thought.. I tried to start with the Count_8_1 project. I follow the README in $IXROOT/src/microace/aces/tutorial1 and use the workbench to build the microACE. This results in a single .uof file, Count_8_1Gig.uof. I copy this to the $IXROOT/bin/arm-be directory, then I run export CONFIG=ARM_BE and make the code. I modify the ixsys.config file to use interface 0-3 and mode=0, then I copy it to $IXROOT/bin/arm-be. That's it. The output when I run ./ixstart on the board outputs: <snip> ConfigureFBusInterface: ENP has 64Bit IXbus. ConfigureFBusInterface: ENP has 64Bit IXbus. ixconfig: Initialized Resource Manager ixconfig: ix_task_init successful ixconfig: Created OSSL thread ixconfig: ix_res_open_sync successful ixconfig: ix_ns_open_sync successful ixconfig: File ./SlowIngressCount.uof doesn't Exist or doesn't have READ permission. </snip> I have searched all over for the file and the permissions are all set correctly. Now, where can I find this file? What am I doing wrong. I can't seem to run any other aces either. I tried the l3forward, but then I only get ixconfig: Invalid port number 2, even though the config file specifies the four first ports. Can anyone help? Please! I've been sitting all day. By the way sometimes the serial connection hangs during setup, after the kernel is loaded. Is there a better way for rebooting the card than rebooting the host? In advance thanks.. -- Øyvind Hvamstad

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Peculiar drops. (quiz)
by Yannis Haritakis 11 Jul '03

11 Jul '03

Hi all, I ran into the following trouble recently, and the "solution" was quite surprising! Let me spend a few lines to describe the environment: I have an ENP2506 board hosted inside a Dell server. One of the Gigabit ports of the ENP2506 is connected to a transmiter, that generates large packets at a constant rate (about 600 Mbit/s). Now, I log into the linux running on the ENP2506. I use the load utility (from the ASAN drivers) to upload some simple code to the uEngines. The uploaded code simply transfers incoming packets from the gigabit port to the RFIFO and then to SDRAM. I use a simple utilitity to read the counters of the gigabit port, and see how many packets were dropped and how many packets were received correctly. This utility uses the ioctls defined in the giga_drv module. One could expect that running at 600Mbit/s should be quite ok, and never loose a single packet. Indeed, this is the case when I move packets from the buffer of the port up to the RFIFO, but not into SDRAM. That is the uploaded code has commented out the sdram2rfifo directive. Everything works fine, and whenever I run my utility it reads zero drops from the counters of the port. Now, I modify the uploaded code so as to perform the final move of data. So data move from the port to the RFIFO and then to SDRAM. In simulation the buffer of the gigabit port never exceeds 200 bytes, using 166MHz core frequence and 66MHz IX Bus frequency.-- well below the actual numbers of the ENP2506 --. And here goes the problem: One, would expect again to have zero drops. However this is not the case, and whenever I ran the utility it reports about 10 to 15 dropped packets, never more. Why ? Hint: I ran the utility again, after I finished writing this email (it took me at least 5 full minutes) and reported 11 drops... :-) yannis

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unable to boot linux on Radisys ENP-2505 (IXP1200 Rev C0)
by Koert Vlaeminck 11 Jul '03

11 Jul '03

Hi, I've been trying to boot a linux kernel on a Radisys ENP-2505 board for some time now. I double-checked just about every software component required, but nothing seemed to resolve my problem. The board reports 'Booting Linux...' and then simply hangs or reboots. Finally I started comparing the content of /dev/bv (using hexdump/hexedit) and the actual content of the IXP memory (using dump/mem in cygmon). If I write a block of 64 bit to /dev/bv on address 0x04008000, only the first 4 bytes (4008000 tot 4008003) are updated, while the last 4 bytes (4008004 to 4008007) become 0. This probably has something to do with the fact that we use the 64bit Radisys ENP-2505 board (IXP1200 Rev C0) on a 32bit PCI system, although we disabled the 64bit PCI extension using the dip switches on the board. However, when we write directly to the IXP memory, all values are updated correctly in /dev/bv. So in summary: * writing from host PC to IXP memory: lower 32 bits of each 64bit block are updated correctly, while the higher 32 bits become 0. * writing to the IXP memory on the cygmon console and then reading its contents through /dev/bv: everything is correct. * 64bit Radisys board is on a 32bit PCI system with the 64bit PCI extension dip switch disabled! (I also tried enabling it, hoping the label was wrong, but that didn't change anything) Do you know of any driver issues regarding this problem? Any suggestions on how to solve it? I tried two seperate ENP-2505 boards and both have the same problem, so I think it's not a hardware problem. And 32bit PCI busses are supported according to the hardware reference. TIA

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How to debug microACE code on hardware?
by Yong Liu 11 Jul '03

11 Jul '03

Hi, I want to add some code into the l3forwarder microace example. Anyone can tell me how can I debug the code on ixp1200 board using the Workbench? I can debug a simple microengine C program on the hardware now. But the microACE code has corelation with the StrongARM code. Thanks! Yong Liu

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IXF1002 : Multipacket mode for IXP12EB
by Yannis Haritakis 09 Jul '03

09 Jul '03

Hi all, Is there anyone that has an IXP 1200 EB development platform (IXP12EB) with the IXF1002 configured with Multipacket mode ON ? Thank you for your time, Yannis Haritakis

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incorrect register live ranges
by Cyrus Hall 08 Jul '03

08 Jul '03

I'm an experiencing what feels like register mis-allocation by uca. I allocate several registers, branch to another segment, allocate several more, and the newly allocated virtual registers end up being allocated in the same physical registers as the virts allocated in before the branch. I'm using an unconditional branch (br) to jump to the second segment (.segment 1) - same to come back to segment 0. IE: .segment 0 .local reg1 immed[reg1, 1] br[label#] done#: ctx_arb[kill] .endlocal .segment 1 label#: .local reg2 immed[reg2, 2] //ends up overwriting reg1 br[done#] .endlocal Does the compiler not calculate virtual live ranges across segments? Or is this a silly .local\.endlocal problem, and the compiler doesn't follow the live range on a branch outside a .local section? thanks, Cy

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I want to get previous IXP1200 mailing-list data
by Cho, joon-woo 08 Jul '03

08 Jul '03

Hello. I want to see previous IXP1200 mailing-list data. Is it opened? If yes, how can I access that information? Thanks.

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Question on SA core memory map
by Wong Kim Sing 08 Jul '03

08 Jul '03

Hi, Recently, I trying to use some location in the sdram to do some buffering, and I come across this problem. In the Microcode Programmer's Reference Manual, under the StrongARM Core Memory Map, the location of the cache flush area is locate at "0xA0000000 - 0xA0004000", and is it supposed to be correct right??? But how come under the file "C:/IXP1200/include/hal_sdram.h", the location is different (0xE0000000 - 0xE0FFFFFF)??? Is anyone know the reason why the location is different? Is the file suppose to be compiled together by SA? Best regard, Mike Mike Wong Kim Sing R&D Engineer Institute for Communications Research 20 Science Park Road TeleTech Park #02-34/37 Singapore Science Park II Singapore 117674 Tel: 65 68729030 DID : 65 68709320 Fax: 65 67795441 Email: wongks(a)icr.a-star.edu.sg Website: http://www.icr.a-star.edu.sg

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[Q] Long question
by Cho, joon-woo 07 Jul '03

07 Jul '03

Hello. I want to install IXP1200EB on Linux-host & I know there are many linux device driver versions. Additionally, is it possible running Linux on StrongARM? In other words, IXP board is operated as computer device & parallel StrongARM core which is resided in IXP can run linux for itself. Is it possible? And if possible, may I get open source like that function? Please give me answers. Thanks.

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[Q] How do I request a command to another PCI device?
by Cho, joon-woo 03 Jul '03

03 Jul '03

Hello. I installed IXP1200EB on the Linux machine with vera driver. And I want to send a command from IXP1200EB to another device. (Especially, SCSI controller or IDE HDD for DMA data transfer from there to IXP1200 SDRAM unti) Is it possible? And if possible, please let me know how I can. Thanks.

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round trip times in workbench
by liam noonan 02 Jul '03

02 Jul '03

Hi, Does anyone know how to configure workbench so that you can write to a file the round trip time for an individual packet (in simulation mode). The logging option does not meet my requirement. I am interested in how long it takes a packet to be received processed and transmitted i..e. an entrance time and exit time. Thanks Liam Noonan University of Limerick Ireland

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[Q] Is there a method to move packet from StrongArm to MAC ports directly?
by Cho, joon-woo 02 Jul '03

02 Jul '03

Hello. I want to know there is direct path from StrongARM to MAC ports. In other words, Can programmer send packets which are managed by StrongARM to the MAC ports not through MicroEngine? Please answer. thanks

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Gbit Receiving using two RFIFO elements per R.Request
by Yannis Haritakis 01 Jul '03

01 Jul '03

Hi all, The following problem was quite hard to discover and still I am not sure it is solved completely. I present it below for comments, suggestions and future use. The problem is around receiving *more* data using speculative receive requests on one gigabit port. The problem raises due to : 1. The default settings of the gigabit controller (IXF1002) (For the ENP2506 and the IXP1200EB using giga_drv.o module) 2. Wrong number of valid bytes reported in RCV_CTL register. 3. Using two RFIFO elements per receive request. The scenario is : 1. Eight threads (2 microEngines) issue speculative receive requests (RR) on one gigabit port in strict order. 2. For each thread, two RFIFO elements are statically assigned. 3. Each RR tries to fill two RFIFO elements. 4. We sent to the gigabit port one packet of 192Bytes (3 MPKTs) 5. We count the number of bytes and the number of MPKTs received The problem : 1. Sometimes we receive 4 MPKTs and the total number of (reported valid) bytes received are more than 192Bytes. The bug: In the ENP2506 the giga_drv.o module configures the gigabit port so as to assert rxvrdy signal when: 1. There are 128B available, OR 2. There is a "header" available. where "header" is defined as the first "headersz" bytes of a packet. By default, headersz is set to 64B long. Therefore, sometimes the rxvrdy signal is asserted when the port buffer has 64B. Then, the Receive State machine tries to fill 2 RFIFO elements from the data that exists in the port buffer. For sure, there are sufficient data to fill one RFIFO element. However, the second element may not be filled completely with valid data. The RCV_CNTL register, however, erroneously reports: 1. That two elements where filled, 2. That all bytes of the second element are valid. I checked the contents of the second RFIFO and found that the last 16 bytes were replicas of the last four correctly received bytes of the second MPKT. That is, if the MPKT in longwords was : ABCD EFGH IJKL MNOP, the received was : ABCD EFGH IJKL KLKL. The solution was to set the "headersz" value to 128B. Another solution would be to set the port not to signal rxvrdy when the header is available, however the driver giga_drv.o needs to be modified so as to allow the chacge of the specific bit of the port_mode register. That's all, Yannis Haritakis, www.ics.forth.gr www.csd.uoc.gr

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RE: [ixp1200] HashSv functions? (accessing the hash units from t he SA)
by Griffin, Chris 26 Jun '03

26 Jun '03

Cyrus, On my installation of the Intel Developer's Workbench, the hashsv.h file is in C:\IXP1200\include --Chris Griffin Embedded Software Engineer Visual Networks, Inc. cgriffin(a)visualnetworks.com phone: 301-296-2644 fax: 301-296-2303 > -----Original Message----- > From: Cyrus Hall [SMTP:hallcp@cs.colorado.edu] > Sent: Thursday, June 26, 2003 4:27 PM > To: ixp1200 List > Subject: [ixp1200] HashSv functions? (accessing the hash units from > the SA) > > I'm in need of a way to initialize a hashtable for the microengines > later use. There appears to be no direct way to access the hash unit on > the FBI, but the Microcode Software Reference Manual lists a family of > functions called HashSv_* (HashSv_Init, etc). The manual lists the > prototypes as being in hashsv.h. > > Yet I can't find hashsv.h anywhere. Is this another documented, but > nonexistent piece of functionality? And if this is the case, how would > people suggest initializing a hash table on the SA for use by the > micros? The values to initialize the table will be coming from a > configuration file, so hard-coding the table in the ME's doesn't work > for me. > > Thanks all, > Cyrus

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HashSv functions? (accessing the hash units from the SA)
by Cyrus Hall 26 Jun '03

26 Jun '03

I'm in need of a way to initialize a hashtable for the microengines later use. There appears to be no direct way to access the hash unit on the FBI, but the Microcode Software Reference Manual lists a family of functions called HashSv_* (HashSv_Init, etc). The manual lists the prototypes as being in hashsv.h. Yet I can't find hashsv.h anywhere. Is this another documented, but nonexistent piece of functionality? And if this is the case, how would people suggest initializing a hash table on the SA for use by the micros? The values to initialize the table will be coming from a configuration file, so hard-coding the table in the ME's doesn't work for me. Thanks all, Cyrus

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Data transfer ,SDRAM
by Prashanth Ramaprasad 26 Jun '03

26 Jun '03

Hi, I have a very basic situation to start off my work on IXP1200. All I want to do is transfer data in blocks (say 1M) from the SDRAM to SRAM, efficiently. Could any of you help me with this hitch. Thank you, Prashanth. _________________________________________________________________ Tired of spam? Get advanced junk mail protection with MSN 8. http://join.msn.com/?page=features/junkmail

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None
by Prashanth Ramaprasad 25 Jun '03

25 Jun '03

Hi there, I recently started working on IXP1200 assembly. During my initial drudge, I was nailed down by this error >> Ref count starting at xfer reg, "$$sdram_reg" does not completely map into a previously specified contiguous region of xfer regs. I'm sure I'm missing something very fundamental. Could any of you help me out of this. Also could you tell me how to access the archives . Thank you, Prashanth. _________________________________________________________________ Add photos to your messages with MSN 8. Get 2 months FREE*. http://join.msn.com/?page=features/featuredemail

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C-Compiler with Optimizations and ua_get/ua_set
by Robert Klima 24 Jun '03

24 Jun '03

Hi, everyone wants lean and fast code, so do I. :) Unfortunately the IXA SDK C-Compiler refuses to properly compile the ua_get/ua_set instructions when optimization ist turned on (-O switch set for example via workbench Build:Settings:C-Compiler:Optimize:Speed). The ua_get/ua_set instructions lead to compile time errors like this : "Unable to determine memory region for ua_set" This does not happen when the compiler is told not to do optimization, so I suspect it to be a bug. The unoptimized code is far bigger (tested with ua_get/ua_set commented out) and innapropriate for serious testing. As I suspect unaligned access to be a common thing here my question into the round : Anyone seen this, too ? And more important - howto overcome this Problem ? By the way - switching to assembly code is not an option to me. ;) Example follows : #include "ixp.h" void main (void) { __declspec(sdram) long long *ptr; ua_set_16(ptr,0,1234); } void exit (unsigned int arg) { } With best regards and thanks in advance. Yours, Robert Klima.

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Re: [ixp1200] Receive error from giga port
by Wong Kim Sing 23 Jun '03

23 Jun '03

Hi, My work is on IXP1240. Which code are you trying, is it "L3Fw8_1f.ue"? For my case, I try to aggregate packet from FE port to GE port, and I have modified the reciving part of the FE code to transmit packet to GE port. Recently, I got a email regarding this problem, and it he said that it is due to the coordination issue in the TFIFO. Do you have any ideal on this issue? As what I suspect, it may be cause by the HW at the TFIFO. Hope we can help each other in solving this problem. Mike Wong Kim Sing R&D Engineer Institute for Communications Research 20 Science Park Road TeleTech Park #02-34/37 Singapore Science Park II Singapore 117674 Tel: 65 68729030 DID : 65 68709320 Fax: 65 67795441 Email: wongks(a)icr.a-star.edu.sg Website: http://www.icr.a-star.edu.sg >>> haritak(a)ics.forth.gr 06/23/03 08:00 AM >>> I am facing exactly the same problem and I haven't found a solution yet. I am working on ENP-2506. In my case the problem is : I move some data to SDRAM (one packet) and then I transmit it several times. What I observe is that some replicas of the packet are xmited fine, while sometimes bits are missing resulting in a smaller packet. The "phenomenon" seems quite periodic: 4 packets received fine, one packet reduced by 63Bytes, 4 packets received fine, one packet reduced by 103Bytes, 4 packets received fine, one packet reduced by 63Bytes, ... The bigger the packet (>15 MPKTs) the more frequent the errors. Smaller packets seem to be fine, however for 8MPKTS still I received one erroneous after some transmissions. I suspect there might be a chance of overflowding the xmit buffer on the port. However, the problem persisted even when the microCode was programmed to xmit only one packet and I was uploading it many times manually in order to produce replicas of the packet. But I am still working on that. So any (debugging) ideas are welcome. Thanks a lot for your time! Yannis Haritakis On Tue, 27 May 2003, Wong Kim Sing wrote: > Hi, > > I had this problem of receiving error packet from the giga port, here is how the test go. > > I had created some packets in the microengine, e.g. > > move($$dxfer0, 0xfffffff1) > move($$dxfer1, 0xfffffff3) > move($$dxfer2, 0xfffffff5) > move($$dxfer3, 0xfffffff7) > move($$dxfer4, 0xfffffff9) > move($$dxfer5, 0xfffffffb) > move($$dxfer6, 0xfffffffd) > move($$dxfer7, 0xffffffff) > > sdram[write, $$dxfer0, packet_buf_addr, 0, 4], ctx_swap > > move($$dxfer0, 0xfffffff1) > move($$dxfer1, 0xfffffff3) > move($$dxfer2, 0xfffffff5) > move($$dxfer3, 0xfffffff7) > move($$dxfer4, 0xfffffff9) > move($$dxfer5, 0xfffffffb) > move($$dxfer6, 0xfffffffd) > move($$dxfer7, 0xffffffff) > > sdram[write, $$dxfer0, packet_buf_addr, 4, 4], ctx_swap > > And I send out this packet to the giga port using the "L3fw8_1.uc" microcode from intel reference design. > > Result obtained as below: > > 19:21:03.445227 ff:f0:ff:ff:ff:f1 ff:ff:ff:f1:ff:ff ffff 116: > > fff2 ffff fff5 ffff fff4 ffff fff5 ffff > fff6 ffff fff9 ffff fff8 ffff fff9 ffff > fffa ffff fffd ffff fffc ffff fffd ffff > fffe ffff fff1 ffff fff0 ffff fff1 ffff > fff2 ffff fff5 ffff fff4 ffff fff5 ffff > fff6 > > On the first row and the fifth row, it should be "fff3" and "fff5" respectively, but it become "fff2" and "fff4", there is one bit being modified. > > And also from 2nd row onward,there is some duplication occur, the 2 words "ffff fff5" has been repeated two time in row 4 and row 6. > > Is there anyone has this similar problem before or do you have any ideal of solving this, please send a email, thank you. > > Mike Wong Kim Sing > R&D Engineer > Institute for Communications Research > 20 Science Park Road > TeleTech Park > #02-34/37 > Singapore Science Park II > Singapore 117674 > Tel: 65 68729030 DID : 65 68709320 > Fax: 65 67795441 > Email: wongks(a)i2r.a-star.edu.sg > Website: http://www.i2r.a-star.edu.sg > >

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