- ixp1200 - lists.cs.princeton.edu

RE: [ixp1200] 1K or 2K instruction cache?
by Tim Stevens 15 Mar '04

15 Mar '04

Hi Jim, And can you tell me how we can do that? Or how we tell the compiler to branch to the second store? Thanks! Regards, Tim At 17:33 15/03/2004, you wrote: >If you have the version of 1200 that contains 2k of instruction memory >you can have upto 2k of instructions. But the instructions are stored >in two separate 1k areas and you need to branch between the two areas. > >-----Original Message----- >From: Tim Stevens [mailto:tim.stevens@intec.ugent.be] >Sent: Monday, March 15, 2004 11:28 AM >To: ixp1200(a)lists.cs.princeton.edu >Subject: [ixp1200] 1K or 2K instruction cache? > > >Hi all, > >We use a RadiSys ENP-2505 board and encounter a problem concerning the >microengine instruction cache size. >Each time we compile the code, the compiler complains that it doesn't fit >into the instruction memory (total size between 1K and 2K instructions), >while our RadiSys documentation states that we have a 2K instruction >cache... >Does this mean that we have to set a specific compiler flag, or is one >instruction larger than one unit in the instruction cache (meaning that a >2K cache can only hold about 1K instructions)? > >Any help would be appreciated. > >Kind regards, > >Tim > >_______________________________________________ >ixp1200 mailing list >ixp1200(a)lists.cs.princeton.edu >https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 > > > - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - >This e-mail and any attachments may contain information which is >confidential, proprietary, privileged or otherwise protected by law. The >information is solely intended for the named addressee (or a person >responsible for delivering it to the addressee). If you are not the >intended recipient of this message, you are not authorized to read, print, >retain, copy or disseminate this message or any part of it. If you have >received this e-mail in error, please notify the sender immediately by >return e-mail and delete it from your computer. > >_______________________________________________ >ixp1200 mailing list >ixp1200(a)lists.cs.princeton.edu >https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

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RE: [ixp1200] need some header files
by Johnson, Erik J 15 Mar '04

15 Mar '04

ixp.h should be in ixp1200\uEngineC\include. I don't know of a CSR.h or buffer.h in the IXA SDK 2.0. However, files with the same name are included with the IXP1200 Programming book CD-ROM. CSR.h is in the Common\ directory and buffer.h is in many of the ChapterXX\ directories. I'll send these separate to you. erik ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Erik J. Johnson Intel Research & Development erik.j.johnson(a)intel.com NOT SPEAKING FOR INTEL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----Original Message----- From: ixp1200-bounces(a)lists.cs.princeton.edu [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of Rajas Raut Sent: Monday, March 15, 2004 6:01 PM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] need some header files Dear All I need three header files of IXP 1200 SDK . ixp.h, CSR.h and buffer.h if anybody can send it to me ...I will be highly thankful.. I need these files for a project of mine. Regards Rajas Raut www.rajasraut.cjb.net

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RE: [ixp1200] 1K or 2K instruction cache?
by Johnson, Erik J 15 Mar '04

15 Mar '04

Yes, for the assembler one must insert the unconditional branches across the 1K boundary. For microC, I believe the compiler will only insert such branches at function boundaries. So, if you are forcing all of your functions to be inlined, main() may become larger than 1K instructions. I have had this problem before and the simple fix is to not inline one or more routines to allow the compiler to place them in a different segment from the "scope" of main(). erik -----Original Message----- From: ixp1200-bounces(a)lists.cs.princeton.edu [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of Elsenbeck, Jim Sent: Monday, March 15, 2004 8:34 AM To: 'IXP1200 Developer's List' Subject: RE: [ixp1200] 1K or 2K instruction cache? If you have the version of 1200 that contains 2k of instruction memory you can have upto 2k of instructions. But the instructions are stored in two separate 1k areas and you need to branch between the two areas. -----Original Message----- From: Tim Stevens [mailto:tim.stevens@intec.ugent.be] Sent: Monday, March 15, 2004 11:28 AM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] 1K or 2K instruction cache? Hi all, We use a RadiSys ENP-2505 board and encounter a problem concerning the microengine instruction cache size. Each time we compile the code, the compiler complains that it doesn't fit into the instruction memory (total size between 1K and 2K instructions), while our RadiSys documentation states that we have a 2K instruction cache... Does this mean that we have to set a specific compiler flag, or is one instruction larger than one unit in the instruction cache (meaning that a 2K cache can only hold about 1K instructions)? Any help would be appreciated. Kind regards, Tim _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer. _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

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RE: [ixp1200] 1K or 2K instruction cache?
by Elsenbeck, Jim 15 Mar '04

15 Mar '04

If you have the version of 1200 that contains 2k of instruction memory you can have upto 2k of instructions. But the instructions are stored in two separate 1k areas and you need to branch between the two areas. -----Original Message----- From: Tim Stevens [mailto:tim.stevens@intec.ugent.be] Sent: Monday, March 15, 2004 11:28 AM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] 1K or 2K instruction cache? Hi all, We use a RadiSys ENP-2505 board and encounter a problem concerning the microengine instruction cache size. Each time we compile the code, the compiler complains that it doesn't fit into the instruction memory (total size between 1K and 2K instructions), while our RadiSys documentation states that we have a 2K instruction cache... Does this mean that we have to set a specific compiler flag, or is one instruction larger than one unit in the instruction cache (meaning that a 2K cache can only hold about 1K instructions)? Any help would be appreciated. Kind regards, Tim _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer.

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1K or 2K instruction cache?
by Tim Stevens 15 Mar '04

15 Mar '04

Hi all, We use a RadiSys ENP-2505 board and encounter a problem concerning the microengine instruction cache size. Each time we compile the code, the compiler complains that it doesn't fit into the instruction memory (total size between 1K and 2K instructions), while our RadiSys documentation states that we have a 2K instruction cache... Does this mean that we have to set a specific compiler flag, or is one instruction larger than one unit in the instruction cache (meaning that a 2K cache can only hold about 1K instructions)? Any help would be appreciated. Kind regards, Tim

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Flash problem with ENP-2505
by vinay kini 15 Mar '04

15 Mar '04

Hi, I'm a beginner using the ENP-2505, and have got myself into a strange (and probably serious) problem. I experimented with the reflash and reprogram commands in the System Monitor, and one of them stopped midway. Now my flash is corrupt. I cannot even load the System Monitor, Cygmon or VxWorks. When I try, there is no response at all from the serial interface, everything just stops (and yeah, the LEDs also stop blinking, which indicates a flash problem). Only the boot manager runs. If I start the Flash Utility, and run FUtil.exe on Windows NT, FUtil terminates saying "No recognized flash types found on board: C5 C5 C5 C5". Please help! Is there a way to reprogram the whole flash? I believe the Flash Utility on the board is still working (along with the Boot Manager). Thanks, Vinay

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A dumb question
by Sanjay Kumar 14 Mar '04

14 Mar '04

Hi Folks, enp2611 (IXP2400) board runs in MPHY-4 mode so it can support up to 4 ports. but enp2611 has only 3 gigabit ports. does this mean the 4th port on enp2611 is unused? or am I missing something? Thanks, Sanjay ---------------------------------- http://www.cc.gatech.edu/~ksanjay/

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New list for IXP2400/IXP2800
by Scott Karlin 10 Mar '04

10 Mar '04

This is to announce the creation of a new list specifically for the discussion on the topic of the IXP2400 and IXP2800 network processors. You may subscribe here: https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx Scott

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Embedded Debugging Utilty
by Prakhyath Makam 09 Mar '04

09 Mar '04

I have configured the ixp1200eb to run in diagnostics mode through hardware jumper settings as well as through the use of BootMgr, but i dont see any EDU diagnostic message display as given in the fig2-2, section 2.4.1 of ixp1200 eval system user guide manual. Moreover , the jumper settings are all set to "factory settings" itself. Am i missing anything here? Please help. Thanking you inanticipation, Prakhyath Makam.

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RE: [ixp1200] Doubt reg. Floating Point Operations support in IXP 1200
by David Mentre 09 Mar '04

09 Mar '04

Hello, > From: romit dasgupta [mailto:romit@myrealbox.com] > Sent: Tuesday, March 09, 2004 6:30 AM [ about doing floating point computations on IXP1200 core ] > If you are talking about userland, then libm is your friend. > If you are > talking about kernel space > then you may compile your kernel with CONFIG_FPE_NWFPE or > CONFIG_FPE_FASTFPE. Romit, I think you have been confused by the fact the CONFIG_FPE_NWFPE and CONFIG_FPE_FASTFPE are kernel options. In fact, once enabled, they provide floating point emulation for *user* application. BTW, if you want fast floating point computations, it appears that there is a patch floating around (no pun intended) for gcc that implements floating point emulation at the compilation toolchain level. According to linux-arm developers, it is much faster than kernel level emulation. However, this patch requires to recompile all the libraries, including the glibc. On 2004-03-08, in an email entitled "SoftFloat Benchmarks" on arm-linux mailing list, Eric BENARD / Free [ebenard(a)free.fr] has posted a comparison of the different solutions: --- email included --- I've run some benchs in order to compare FP solutions on an IXP425 (rev0) running at 533 MHz with Linux 2.4.21-rmk1-ds3 (with NWFPE patches from the arm-kernel ML). Test softwares are : nbench v2 and flops 2.0 Test compilers are : - gcc 3.3.3 + glibc 2.3.2 => using kernel emulation NWFPE or FFPE - gcc 3.3.3 + Nico's patches + glibc 2.3.2 Compiler options are : -O3 -fomit-frame-pointer -mcpu=xscale -mtune=xscale -mbig-endian -static Results : *** nbench, Floating Point Index (vs P90 / vs K6/233) : NWFPE : 0.028 / 0.015 FFPE : 0.062 / 0.031 = NWFPE * 2.2 NICO : 0.260 / 0.144 = NWFPE * 9.3 *** flops, mean of the 4 MFLOPS values returned by the test : NWFPE : 0.52 FFPE : 1.89 = NWFPE * 3.63 NICO : 3.91 = NWFPE * 7.52 --- end of email included --- If you want fast floating point anyway, you'd better do fix point computations on integers. It is not allowed by linux kernel developpers to do floating point computations in the kernel. Sharmila, if you want more information on floating point and arm, look at arm-linux mailing list archive. This has been discussed numerous times. Yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

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