Hi All,
You have Evaluation Systems based on the A-3 step of the IXP1200 Network
Processor. Buried at the bottom of the cover letter included with your
systems is the following:
"Also note, the IXP1200 Network Processor on this evaluation system runs at
a core frequency of 176 MHz. This temporary condition is due to a lack of
component availability used to design the evaluation board."
Intel officially supports 166 MHz and now 200 MHz versions of the IXP1200.
Our first version of the Evaluation System run at 176 MHz as indicated
above.
Susan Yost
IXP1200 Tech Marketing
-----Original Message-----
From: Tammo Spalink [mailto:tspalink@CS.Princeton.EDU]
Sent: Thursday, July 20, 2000 3:58 PM
To: Perry Wagle
Cc: ixp1200(a)CS.Princeton.EDU
Subject: Re: IXP clock rate question
Don't really know what rev board we have. I think it's an A-somthing.
Our numbers might not need to be the same, however, since I am timing
the microengine cycle speed and not the StrongARM.
Tammo
On Thu, 20 Jul 2000, Perry Wagle wrote:
> > Measurements with the microengine cycle counters suggest that the
> > clock speed of our system is 177MHz as opposed to the manual's claim
> > of 166MHz.
> >
> > Does this sound accurate?
>
> I'm including my own observations in my answer to your question:
>
> I'm loading my boot loader from angel on a rev A board. I have the
> RTC firing an interrupt "once a second", and TIMER_1 firing "a hundred
> times a second". Angel has set the PLL_CFG register to (my debugging
> routine dumps "label address value"):
>
> pll_cfg 90000c00 00000010
>
> which I've assumed to be "correct", so haven't tried changing it,
> especially since the documentation warns againts setting it too high.
>
> The RTC uses what I call the "slow clock" (~ 3 MHz), and the TIMER's
> use what I call the "fast clock" (~ 162 Mhz).
>
> To initialize the RTC calibration, I set the RTC_DIV register to my
> slow_clock (expressed in Hz) divided by 128, and currently get:
>
> rtc_div 90002000 00037080
>
> (so RDIV = 0x7080) and to initialized the TIMER_1 calibration, I set
> the TIMER_1_LOAD register to the my fast_clock (expressed in Hz)
> divided by 100, and currently get:
>
> timer_1_load 42000300 0018bff0
> timer_1_control 42000308 000000c0
>
> (notice that the value of timer_1_control shows that I am counting CPU
> cycles without a divisor).
>
> With my slow_clock constant set to 3686400 Hz and my fast_clock
> constant set to 162200000, I am getting approximately 100.15 TIMER_1
> interrupts per RTC interrupt (over a 12 hour period). These two
> values correspond to the ROUNDED values of the two clock rates from
> page 28 of the "IXP1200 Network Processor Specification Update (June
> 2000)". The roundoff is SIGNIFICANT to my measurement, and I wish the
> documentation writers WOULDN'T ROUND OFF THE VALUES. For example,
> since the given value of the fast_clock was almost exactly 44 times
> the given value of the slow_clock, I tried just setting the fast_clock
> to exactly 44 times the slow clock, and got 100.5 TIMER_1 interrupts
> per second. BOTH values of the fast_clock were within the roundoff of
> the value given in the documentation.
>
> My setting of the slow_clock is consistant with the documentation's
> suggestion, and the seconds doesn't skew according to my eyeball's
> comparison with my wristwatch. It's close enough that I'm not going
> to worry more about it more until I have Linux running XNTP.
>
> So my answer to your original question is that I'm somewhat confident
> that I have the Core Clock measured at about 162 MHz (+- 1 Mhz), at
> least with respect to the RTC and TIMER_1 hardware on Rev A hardware.
> Which Rev do you guys have?
>
> -- Perry
>
